The present invention relates to a semiconductor device, and a process for producing the semiconductor device.
Japanese Patent Application Laid-Open No. Hei 1 (1989)-144648 (Patent Document 1) and Japanese Patent Application Laid-Open No. Hei 7 (1995)-273288 (Patent Document 2) disclose that resistance elements of a semiconductor device having bipolar transistors are formed in device isolation regions in order to improve the element-integration degree of the device. According to, for example, Patent Document 1, after each trench is formed in a substrate, a silicon oxide film is formed to be extended from the inside of the trench to the whole of the upper surface of the substrate. Thereafter, a polysilicon which is to be resistance element regions is formed, and the polysilicon is worked to remain in the trench, thereby forming resistance elements.
Japanese Patent Application Laid-Open No. 2001-077189 (Patent Document 3) discloses a technique of locating device isolation regions in a substrate when MOS transistors are formed. The documents states that when the device isolation regions are located in the substrate, a mask is once formed in a region other than element-isolation-forming regions, so as to form the device isolation region, and subsequently the mask is removed by wet etching.